1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
CE#
T
T
DS
CPH
T
AS
OE#
T
CH
WE#
T
CS
DQ
AA
55
A0
DATA
BYTE
7-0
SW0
SW1
SW2
(ADDR/DATA)
1147 F05.1
Note: AMS = Most significant address
MS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
A
Figure 7: CE# Controlled Program Cycle Timing Diagram
ADDRESS A
MS-0
T
CE
CE#
T
T
OES
OEH
OE#
T
OE
WE#
DQ
7
D
D#
D#
D
1147 F06.1
Note: AMS = Most significant address
MS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
A
Figure 8: Data# Polling Timing Diagram
©2013 Silicon Storage Technology, Inc.
DS25022B
04/13
15
MICROCHIP [ MICROCHIP ]
