PIC24FJ64GA104 FAMILY
7.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
7.0
INTERRUPT CONTROLLER
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 8. “Interrupts” (DS39707).
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes will use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The PIC24F interrupt controller reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the PIC24F CPU. It has the following
features:
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the inter-
rupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
• Up to 8 processor exceptions and software traps
• 7 user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
7.2
Reset Sequence
• Alternate Interrupt Vector Table (AIVT) for debug
support
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24F devices clear their registers in response to
a Reset which forces the PC to zero. The micro-
controller then begins program execution at location
000000h. The user programs a GOTOinstruction at the
Reset address, which redirects program execution to
the appropriate start-up routine.
• Fixed interrupt entry and return latencies
7.1
Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 7-1.
The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors, consisting of
8 non-maskable trap vectors, plus up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Note:
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESETinstruction.
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt
associated with vector 0 will take priority over interrupts
at any other vector address.
PIC24FJ64GA104
family
devices
implement
non-maskable traps and unique interrupts. These are
summarized in Table 7-1 and Table 7-2.
2010 Microchip Technology Inc.
DS39951C-page 65
MICROCHIP [ MICROCHIP ]
