PIC24FJ64GA104 FAMILY
REGISTER 7-1:
SR: ALU STATUS REGISTER (IN CPU)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0
DC(1)
bit 15
bit 8
R/W-0
IPL2(2,3)
bit 7
R/W-0
IPL1(2,3)
R/W-0
IPL0(2,3)
R-0
RA(1)
R/W-0
N(1)
R/W-0
OV(1)
R/W-0
Z(1)
R/W-0
C(1)
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111= CPU interrupt priority level is 7 (15). User interrupts are disabled.
110= CPU interrupt priority level is 6 (14)
101= CPU interrupt priority level is 5 (13)
100= CPU interrupt priority level is 4 (12)
011= CPU interrupt priority level is 3 (11)
010= CPU interrupt priority level is 2 (10)
001= CPU interrupt priority level is 1 (9)
000= CPU interrupt priority level is 0 (8)
Note 1: See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control
functions.
2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
REGISTER 7-2:
CORCON: CPU CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0
IPL3(2)
R/W-0
PSV(1)
U-0
—
U-0
—
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 3
IPL3: CPU Interrupt Priority Level Status bit(2)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
Note 1: See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control
functions.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
2010 Microchip Technology Inc.
DS39951C-page 69
MICROCHIP [ MICROCHIP ]
