PIC24FJ64GA104 FAMILY
REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
ACKDT: Acknowledge Data bit (When operating as I2C master. Applicable during master receive.)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1= Sends NACK during Acknowledge
0= Sends ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(When operating as I2C master. Applicable during master receive.)
1= Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware
clear at end of master Acknowledge sequence.
0= Acknowledge sequence is not in progress
bit 3
bit 2
bit 1
RCEN: Receive Enable bit (when operating as I2C master)
1= Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0= Receive sequence is not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1= Initiates Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0= Stop condition is not in progress
RSEN: Repeated Start Condition Enabled bit (when operating as I2C master)
1= Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master
Repeated Start sequence.
0= Repeated Start condition is not in progress
bit 0
SEN: Start Condition Enabled bit (when operating as I2C master)
1= Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0= Start condition is not in progress
2010 Microchip Technology Inc.
DS39951C-page 179
MICROCHIP [ MICROCHIP ]
