PIC18F2480/2580/4480/4580
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580)
Value on Detailson
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
Page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
55, 68
55, 68
55, 68
55, 69
55, 68
55, 68
55, 68
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
bit 21(1)
Return Stack Pointer
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 55, 109
0000 0000 55, 109
0000 0000 55, 109
0000 0000 55, 109
xxxx xxxx 55, 117
xxxx xxxx 55, 117
0000 000x 55, 121
1111 -1-1 55, 122
11-0 0-00 55, 123
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
INTCON
INTCON2
INTCON3
INDF0
GIE/GIEH
RBPU
PEIE/GIEL
INTEDG0
INT1IP
TMR0IE
INTEDG1
—
INT0IE
INTEDG2
INT2IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
INT2IP
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
N/A
N/A
N/A
N/A
55, 96
55, 97
55, 97
55, 97
55, 97
POSTINC0
POSTDEC0
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register), value of
FSR0 offset by W
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
55, 96
55, 96
55
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
55, 96
55, 97
55, 97
55, 97
55, 97
POSTINC1
POSTDEC1
PREINC1
PLUSW1
N/A
N/A
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register), value of
FSR1 offset by W
N/A
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High
---- xxxx
xxxx xxxx
---- 0000
N/A
55, 96
55, 96
56, 73
56, 96
56, 97
56, 97
56, 97
56, 97
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
BSR
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
POSTINC2
POSTDEC2
PREINC2
PLUSW2
N/A
N/A
N/A
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register), value of
FSR2 offset by W
N/A
Legend: x= unknown, u= unchanged, -= unimplemented, q= value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.
© 2009 Microchip Technology Inc.
DS39637D-page 83