PIC18F2480/2580/4480/4580
FIGURE 19-7:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit 0
bit 7/8
bit 0 bit 1
bit 7/8
Stop
bit
Stop
bit
Stop
bit
bit 7/8
Rcv Shift Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word
causing the OERR (overrun) bit to be set.
TABLE 19-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
CCP1IF
INT0IF
RBIF
55
58
58
58
57
57
57
57
57
57
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
TMR2IF TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
TXIP
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
CREN
FERR
OERR
RX9D
EUSART Receive Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDOVF
RCIDL
ABDEN
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in PIC18F2X80 devices; always maintain these bits clear.
© 2009 Microchip Technology Inc.
DS39637D-page 245
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