PIC18F2480/2580/4480/4580
FIGURE 19-3:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
8
TXIE
MSb
(8)
LSb
0
Pin Buffer
and Control
•
• •
TSR Register
TX Pin
Interrupt
Baud Rate CLK
SPBRG
TXEN
TRMT
SPEN
BRG16
SPBRGH
TX9
TX9D
Baud Rate Generator
FIGURE 19-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX
(pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 19-5:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TX
(pin)
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
1 TCY
Word 1
TXIF bit
(Interrupt Reg. Flag)
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
This timing diagram shows two consecutive transmissions.
DS39637D-page 242
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
