PIC18F2480/2580/4480/4580
FIGURE 19-12:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 19-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
ADDEN
TMR0IF
INT0IF
RBIF
55
58
58
58
57
57
57
57
57
57
PSPIF(1)
PSPIE(1)
PSPIP(1)
SPEN
ADIF
ADIE
ADIP
RX9
RCIF
RCIE
RCIP
SREN
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
TXIE
IPR1
TXIP
RCSTA
TXREG
TXSTA
CREN
FERR
OERR
RX9D
EUSART Transmit Register
CSRC
TX9
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
BAUDCON ABDOVF
RCIDL
ABDEN
SPBRGH
SPBRG
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in PIC18F2X80 devices; always maintain these bits clear.
© 2009 Microchip Technology Inc.
DS39637D-page 249
MICROCHIP [ MICROCHIP ]
