欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F2450-I/SO的Datasheet PDF文件第130页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第131页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第132页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第133页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第135页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第136页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第137页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第138页  
PIC18F2450/4450  
REGISTER 14-2: UCFG: USB CONFIGURATION REGISTER  
R/W-0  
R/W-0  
UOEMON(1)  
U-0  
R/W-0  
UPUEN(2,3) UTRDIS(2)  
R/W-0  
R/W-0  
FSEN(2)  
R/W-0  
PPB1  
R/W-0  
PPB0  
UTEYE  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
bit 6  
UTEYE: USB Eye Pattern Test Enable bit  
1= Eye pattern test enabled  
0= Eye pattern test disabled  
UOEMON: USB OE Monitor Enable bit(1)  
1= UOE signal active; it indicates intervals during which the D+/D- lines are driving  
0= UOE signal inactive  
bit 5  
bit 4  
Unimplemented: Read as ‘0’  
UPUEN: USB On-Chip Pull-up Enable bit(2,3)  
1= On-chip pull-up enabled (pull-up on D+ with FSEN = 1or D- with FSEN = 0)  
0= On-chip pull-up disabled  
bit 3  
UTRDIS: On-Chip Transceiver Disable bit(2)  
1= On-chip transceiver disabled; digital transceiver interface enabled  
0= On-chip transceiver active  
bit 2  
FSEN: Full-Speed Enable bit(2)  
1= Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz  
0= Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz  
bit 1-0  
PPB1:PPB0: Ping-Pong Buffers Configuration bits  
11= Enabled for all endpoints except Endpoint 0  
10= Even/Odd ping-pong buffers enabled for all endpoints  
01= Even/Odd ping-pong buffer enabled for OUT Endpoint 0  
00= Even/Odd ping-pong buffers disabled  
Note 1: If UTRDIS is set, the UOE signal will be active independent of the UOEMON bit setting.  
2: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These  
values must be preconfigured prior to enabling the module.  
3: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.  
There are 6 signals from the module to communicate  
with and control an external transceiver:  
The VPO and VMO signals are outputs from the SIE to  
the external transceiver. The RCV signal is the output  
from the external transceiver to the SIE; it represents  
the differential signals from the serial bus translated  
into a single pulse train. The VM and VP signals are  
used to report conditions on the serial bus to the SIE  
that can’t be captured with the RCV signal. The  
combinations of states of these signals and their  
interpretation are listed in Table 14-1 and Table 14-2.  
• VM: Input from the single-ended D- line  
• VP: Input from the single-ended D+ line  
• RCV: Input from the differential receiver  
• VMO: Output to the differential line driver  
• VPO: Output to the differential line driver  
• UOE: Output enable  
DS39760A-page 132  
Advance Information  
© 2006 Microchip Technology Inc.  
 复制成功!