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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
4.4.3  
RC_IDLE MODE  
4.5.2  
EXIT BY WDT TIME-OUT  
In RC_IDLE mode, the CPU is disabled but the periph-  
erals continue to be clocked from the internal oscillator.  
This mode allows for controllable power conservation  
during Idle periods.  
A WDT time-out will cause different actions depending  
on which power-managed mode the device is in when  
the time-out occurs.  
If the device is not executing code (all Idle modes and  
Sleep mode), the time-out will result in an exit from the  
power-managed mode (see Section 4.2 “Run  
Modes” and Section 4.3 “Sleep Mode”). If the device  
is executing code (all Run modes), the time-out will  
result in a WDT Reset (see Section 21.2 “Watchdog  
Timer (WDT)”).  
From RC_RUN, this mode is entered by setting the  
IDLEN bit and executing a SLEEP instruction. If the  
device is in another Run mode, first set IDLEN, then  
clear the SCS bits and execute SLEEP. When the clock  
source is switched to the INTRC, the primary oscillator  
is shut down and the OSTS bit is cleared.  
When a wake event occurs, the peripherals continue to  
be clocked from the INTRC. After a delay of TCSD  
following the wake event, the CPU begins executing  
code being clocked by the INTRC. The IDLEN and  
SCS bits are not affected by the wake-up. The INTRC  
source will continue to run if either the WDT or the  
Fail-Safe Clock Monitor is enabled.  
The WDT timer and postscaler are cleared by one of  
the following events:  
• executing a SLEEPor CLRWDTinstruction  
• the loss of a currently selected clock source (if the  
Fail-Safe Clock Monitor is enabled)  
4.5.3  
EXIT BY RESET  
Exiting an Idle or Sleep mode by Reset automatically  
forces the device to run from the INTRC.  
4.5  
Exiting Idle and Sleep Modes  
An exit from Sleep mode, or any of the Idle modes, is  
triggered by an interrupt, a Reset or a WDT time-out.  
This section discusses the triggers that cause exits  
from power-managed modes. The clocking subsystem  
actions are discussed in each of the power-managed  
modes sections (see Section 4.2 “Run Modes”,  
Section 4.3 “Sleep Mode” and Section 4.4 “Idle  
Modes”).  
4.5.4  
EXIT WITHOUT AN OSCILLATOR  
START-UP DELAY  
Certain exits from power-managed modes do not  
invoke the OST at all. There are two cases:  
• PRI_IDLE mode where the primary clock source  
is not stopped; and  
• the primary clock source is the EC mode.  
4.5.1  
EXIT BY INTERRUPT  
In these instances, the primary clock source either  
does not require an oscillator start-up delay, since it is  
already running (PRI_IDLE), or normally does not  
require an oscillator start-up delay (EC). However, a  
fixed delay of interval, TCSD, following the wake event  
is still required when leaving Sleep and Idle modes to  
allow the CPU to prepare for execution. Instruction  
execution resumes on the first clock cycle following this  
delay.  
Any of the available interrupt sources can cause the  
device to exit from an Idle mode, or the Sleep mode, to  
a Run mode. To enable this functionality, an interrupt  
source must be enabled by setting its enable bit in one  
of the INTCON or PIE registers. The exit sequence is  
initiated when the corresponding interrupt flag bit is set.  
On all exits from Idle or Sleep modes by interrupt, code  
execution branches to the interrupt vector if the  
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code  
execution continues or resumes without branching  
(see Section 9.0 “Interrupts”).  
A fixed delay of interval, TCSD, following the wake event  
is required when leaving Sleep and Idle modes. This  
delay is required for the CPU to prepare for execution.  
Instruction execution resumes on the first clock cycle  
following this delay.  
DS39682E-page 40  
© 2009 Microchip Technology Inc.  
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