PIC18F45J10 FAMILY
5.1
RCON Register
5.0
RESET
Device Reset events are tracked through the RCON
register (Register 5-1). The lower six bits of the register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be set by the event and
must be cleared by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 5.7 “Reset State
of Registers”.
The PIC18F45J10 family of devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Configuration Mismatch (CM)
f) Brown-out Reset (BOR)
g) RESETInstruction
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
h) Stack Full Reset
i) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.4.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 21.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESETInstruction
Configuration Word Mismatch
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLR
( )_IDLE
Sleep
WDT
Time-out
POR Pulse
VDD Rise
Detect
VDD
Brown-out
Reset
(1)
S
PWRT
Chip_Reset
32 μs
PWRT
66 ms
R
Q
11-Bit Ripple Counter
INTRC
Note 1: The Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.
© 2009 Microchip Technology Inc.
DS39682E-page 41
MICROCHIP [ MICROCHIP ]
