欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第36页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第37页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第38页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第39页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第41页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第42页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第43页浏览型号PIC18F25J10-I/SS的Datasheet PDF文件第44页  
PIC18F45J10 FAMILY  
4.3  
Sleep Mode  
4.4  
Idle Modes  
The power-managed Sleep mode is identical to the  
legacy Sleep mode offered in all other PIC micro-  
controllers. It is entered by clearing the IDLEN bit (the  
default state on device Reset) and executing the  
SLEEP instruction. This shuts down the selected  
oscillator (Figure 4-4). All clock source status bits are  
cleared.  
The Idle modes allow the controller’s CPU to be  
selectively shut down while the peripherals continue to  
operate. Selecting a particular Idle mode allows users  
to further manage power consumption.  
If the IDLEN bit is set to a ‘1’ when a SLEEPinstruction is  
executed, the peripherals will be clocked from the clock  
source selected using the SCS<1:0> bits; however, the  
CPU will not be clocked. The clock source status bits are  
not affected. Setting IDLEN and executing a SLEEP  
instruction provides a quick method of switching from a  
given Run mode to its corresponding Idle mode.  
Entering the Sleep mode from any other mode does not  
require a clock switch. This is because no clocks are  
needed once the controller has entered Sleep. If the  
WDT is selected, the INTRC source will continue to  
operate. If the Timer1 oscillator is enabled, it will also  
continue to run.  
If the WDT is selected, the INTRC source will continue  
to operate. If the Timer1 oscillator is enabled, it will also  
continue to run.  
When a wake event occurs in Sleep mode (by interrupt,  
Reset or WDT time-out), the device will not be clocked  
until the clock source selected by the SCS<1:0> bits  
becomes ready (see Figure 4-5), or it will be clocked  
from the internal oscillator if either the Two-Speed  
Start-up or the Fail-Safe Clock Monitor are enabled  
(see Section 21.0 “Special Features of the CPU”). In  
either case, the OSTS bit is set when the primary clock  
is providing the device clocks. The IDLEN and SCS bits  
are not affected by the wake-up.  
Since the CPU is not executing instructions, the only  
exits from any of the Idle modes are by interrupt, WDT  
time-out or a Reset. When a wake event occurs, CPU  
execution is delayed by an interval of TCSD  
(parameter 38, Table 24-10) while it becomes ready to  
execute code. When the CPU begins executing code,  
it resumes with the same clock source for the current  
Idle mode. For example, when waking from RC_IDLE  
mode, the internal oscillator block will clock the CPU  
and peripherals (in other words, RC_RUN mode). The  
IDLEN and SCS bits are not affected by the wake-up.  
While in any Idle mode or the Sleep mode, a WDT  
time-out will result in a WDT wake-up to the Run mode  
currently specified by the SCS<1:0> bits.  
FIGURE 4-4:  
TRANSITION TIMING FOR ENTRY TO SLEEP MODE  
Q1 Q2 Q3 Q4 Q1  
OSC1  
CPU  
Clock  
Peripheral  
Clock  
Sleep  
Program  
Counter  
PC  
PC + 2  
FIGURE 4-5:  
TRANSITION TIMING FOR WAKE FROM SLEEP  
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
Q2 Q3 Q4 Q1 Q2  
Q1  
OSC1  
(1)  
TOST  
CPU Clock  
Peripheral  
Clock  
Program  
Counter  
PC  
OSTS bit Set  
PC + 2  
PC + 4  
PC + 6  
Wake Event  
Note1: TOST = 1024 TOSC. These intervals are not shown to scale.  
DS39682E-page 38  
© 2009 Microchip Technology Inc.  
 复制成功!