PIC18F45J10 FAMILY
2
16.4.1
REGISTERS
16.4 I C Mode
The MSSP module has six registers for I2C operation.
These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
• MSSP Control Register 1 (SSPxCON1)
• MSSP Control Register 2 (SSPxCON2)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
Two pins are used for data transfer:
• MSSP Shift Register (SSPxSR) – Not directly
accessible
• Serial clock (SCLx) – RC3/SCK1/SCL1 or
RD6/SCK2/SCL2
• MSSP Address Register (SSPxADD)
• Serial data (SDAx) – RC4/SDI1/SDA1 or
RD5/SDI2/SDA2
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I2C mode operation. The
SSPxCON1 and SSPxCON2 registers are readable
and writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
The user must configure these pins as inputs by setting
the associated TRIS bits.
FIGURE 16-7:
MSSP BLOCK DIAGRAM
(I2C™ MODE)
Many of the bits in SSPxCON2 assume different
functions, depending on whether the module is operat-
ing in Master or Slave mode; bits<5:2> also assume
different names in Slave mode. The different aspects of
SSPxCON2 are shown in Register 16-5 (for Master
mode) and Register 16-6 (Slave mode).
Internal
Data Bus
Read
Write
SSPxBUF reg
SCLx
SDAx
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data bytes
are written to or read from.
Shift
Clock
SSPxADD register holds the slave device address
when the MSSP is configured in I2C Slave mode. When
the MSSP is configured in Master mode, the lower
seven bits of SSPxADD act as the Baud Rate
Generator reload value.
SSPxSR reg
LSb
MSb
Match Detect
Addr Match
Address Mask
In receive operations, SSPxSR and SSPxBUF together
create a double-buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
SSPxADD reg
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
Set, Reset
Start and
S, P bits
Stop bit Detect
(SSPxSTAT reg)
Note:
Disabling the MSSP module by clearing
the SSPEN (SSPxCON1<5>) bit may not
reset the module. It is recommended to
clear the SSPxSTAT, SSPxCON1 and
SSPxCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
© 2009 Microchip Technology Inc.
DS39682E-page 159
MICROCHIP [ MICROCHIP ]
