PIC18F45J10 FAMILY
16.3.8
OPERATION IN POWER-MANAGED
MODES
16.3.10 BUS MODE COMPATIBILITY
Table 16-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of Sleep mode, all clocks are halted.
TABLE 16-1: SPI BUS MODES
In Idle modes, a clock is provided to the peripherals.
That clock should be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTOSC source. See Section 3.6 “Clock Sources
and Oscillator Switching” for additional information.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
There is also an SMP bit which controls when the data
is sampled.
16.3.11 SPI CLOCK SPEED AND MODULE
INTERACTIONS
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
Because MSSP1 and MSSP2 are independent
modules, they can operate simultaneously at different
data rates. Setting the SSPM<3:0> bits of the
SSPxCON1 register determines the rate for the
corresponding module.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set
and if enabled, will wake the device.
An exception is when both modules use Timer2 as a
time base in Master mode. In this instance, any
changes to the Timer2 operation will affect both MSSP
modules equally. If different bit rates are required for
each module, the user should select one of the other
three time base options for one of the modules.
16.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
© 2009 Microchip Technology Inc.
DS39682E-page 157
MICROCHIP [ MICROCHIP ]
