PIC18F45J10 FAMILY
TABLE 16-2: REGISTERS ASSOCIATED WITH SPI OPERATION
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Values
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Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
TXIE
TXIP
—
RBIE
SSP1IF
SSP1IE
SSP1IP
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
—
INT0IF
RBIF
47
49
49
49
49
49
49
50
50
50
48
48
48
50
50
50
PSPIF(1)
PSPIE(1)
PSPIP(1)
SSP2IF
SSP2IE
SSP2IP
—
ADIF
ADIE
RCIF
RCIE
RCIP
—
TMR2IF
TMR1IF
PIE1
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
ADIP
PIR3
BCL2IF
BCL2IE
BCL2IP
—
—
—
—
—
PIE3
—
—
—
—
IPR3
—
—
—
—
—
—
TRISA
TRISC
TRISD(1)
TRISA5
TRISC5
TRISD5
—
TRISA3
TRISC3
TRISD3
TRISA2
TRISC2
TRISD2
TRISA1
TRISC1
TRISD1
TRISA0
TRISC0
TRISD0
TRISC7
TRISD7
TRISC6
TRISD6
TRISC4
TRISD4
SSP1BUF MSSP1 Receive Buffer/Transmit Register
SSP1CON1 WCOL
SSP1STAT SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
SSP2BUF MSSP2 Receive Buffer/Transmit Register
SSP2CON1 WCOL
SSP2STAT SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
Legend: Shaded cells are not used by the MSSP module in SPI mode.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682E-page 158
© 2009 Microchip Technology Inc.
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