PIC18F45J10 FAMILY
SDOx pin is driven. When the SSx pin goes high, the
SDOx pin is no longer driven, even if in the middle of a
transmitted byte and becomes a floating output.
External pull-up/pull-down resistors may be desirable
depending on the application.
16.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCKx. When the
last bit is latched, the SSPxIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCKx pin. The Idle
state is determined by the CKP bit (SSPxCON1<4>).
Note 1: When the SPI is in Slave mode with SSx pin
control enabled (SSPxCON1<3:0> = 0100),
the SPI module will reset if the SSx pin is set
to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCKx pin. This
external clock must meet the minimum high and low
times as specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SSx pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SSx pin to
a high level or clearing the SSPEN bit.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
To emulate two-wire communication, the SDOx pin can
be connected to the SDIx pin. When the SPI needs to
operate as a receiver, the SDOx pin can be configured
as an input. This disables transmissions from the
SDOx. The SDIx can always be left as an input (SDIx
function) since it cannot create a bus conflict.
16.3.7
SLAVE SELECT
SYNCHRONIZATION
The SSx pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SSx pin control
enabled (SSPxCON1<3:0> = 04h). When the SSx pin
is low, transmission and reception are enabled and the
FIGURE 16-4:
SLAVE SYNCHRONIZATION WAVEFORM
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
bit 6
bit 7
bit 7
bit 0
SDOx
bit 7
SDIx
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
Next Q4 Cycle
after Q2
↓
SSPxSR to
SSPxBUF
© 2009 Microchip Technology Inc.
DS39682E-page 155
MICROCHIP [ MICROCHIP ]
