PIC18F45J10 FAMILY
REGISTER 16-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MASTER MODE)
R/W-0
GCEN
R/W-0
R/W-0
ACKDT(1)
R/W-0
ACKEN(2)
R/W-0
RCEN(2)
R/W-0
PEN(2)
R/W-0
RSEN(2)
R/W-0
SEN(2)
ACKSTAT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
GCEN: General Call Enable bit
Unused in Master mode.
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
bit 5
bit 4
ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit(2)
1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
bit 1
bit 0
RCEN: Receive Enable bit (Master Receive mode only)(2)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit(2)
1= Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Stop condition Idle
RSEN: Repeated Start Condition Enable bit(2)
1= Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable bit(2)
1= Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0= Start condition Idle
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).
DS39682E-page 162
© 2009 Microchip Technology Inc.
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