PIC18CXX2
5.2.3
INTERRUPTS
Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
can either be vectored to the high or low priority Inter-
rupt Service Routine (ISR) or continue execution from
where programming commenced.
The long write must be terminated by a reset or any
interrupt.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, program-
ming will terminate. This will occur regardless of the
settings of interrupt priority bits, the GIE/GIEH bit or the
PIE/GIEL bit.
In either case, the interrupt flag will not be cleared
when programming is terminated and will need to be
cleared by the software.
TABLE 5-2:
SLEEP MODE, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
GIE/
GIEH
PIE/
GIEL
Interrupt Interrupt
Priority
Action
Enable
Flag
X
X
0
X
X
0
X
0
X
Long write continues even if interrupt
flag becomes set during sleep.
(default)
X
X
1
0
1
Long write continues, will wake when
the interrupt flag is set.
1
Terminates long write,
(default) (default)
executes next instruction. Interrupt flag
not cleared.
0
1
1
1
1
Terminates long write,
(default)
high priority
(default)
executes next instruction. Interrupt flag
not cleared.
1
0
0
low
1
1
1
1
Terminates long write, executes next
instruction. Interrupt flag not cleared.
(default)
0
1
0
low
Terminates long write, branches to low
priority interrupt vector.
(default)
Interrupt flag can be cleared by ISR.
1
0
1
1
1
Terminates long write, branches to high
priority interrupt vector.
Interrupt flag can be cleared by ISR.
(default) high priority
(default)
DS39026B-page 58
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
