PIC18CXX2
5.1.2
TABLAT - TABLE LATCH REGISTER
address up to 2M bytes of program memory space. The
22nd bit allows access to the Device ID, the User ID
and the Configuration bits.
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data memory.
The table pointer TBLPTR is used by the TBLRD and
TBLWT instructions. These instructions can update
the TBLPTR in one of four ways based on the table
operation. These operations are shown in Table 5-1.
These operations on the TBLPTR only affect the low
order 21-bits.
5.1.3
TBLPTR - TABLE POINTER REGISTER
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper byte, High
byte and Low byte). These three registers (TBLP-
TRU:TBLPTRH:TBLPTRL) join to form a 22-bit wide
pointer. The low order 21-bits allow the device to
TABLE 5-1:
Example
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 55
MICROCHIP [ MICROCHIP ]
