PIC18CXX2
6.2
Operation
EXAMPLE 6-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 6-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
MOVFF
MULWF
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
PRODH:PRODL
;
MOVFF
MOVFF
PRODH, RES1 ;
PRODL, RES0 ;
Example 6-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
;
;
MOVFF
MULWF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
PRODH:PRODL
;
MOVFF
MOVFF
PRODH, RES3 ;
PRODL, RES2 ;
EXAMPLE 6-1: 8 x 8 UNSIGNED MULTIPLY
ROUTINE
MOVFF
MULWF
ARG1, WREG
ARG2
;
MOVFF
MULWF
ARG1L, WREG
ARG2H
; ARG1 * ARG2 ->
; ARG1L * ARG2H ->
;
PRODH:PRODL
;
PRODH:PRODL
MOVFF
ADDWF
MOVFF
ADDWFC
CLRF
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
EXAMPLE 6-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
RES2, F
WREG, F
RES3, F
;
;
;
MOVFF
MULWF
ARG1, WREG
ARG2
ADDWFC
; ARG1 * ARG2 ->
; PRODH:PRODL
;
MOVFF
MULWF
ARG1H, WREG ;
ARG2L ; ARG1H * ARG2L ->
BTFSC
SUBWF
ARG2, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
PRODH:PRODL
;
- ARG1
MOVFF
ADDWF
MOVFF
ADDWFC
CLRF
PRODL, WREG ;
MOVFF
BTFSC
SUBWF
ARG2, WREG
ARG1, SB
PRODH, F
RES1, F
; Add cross
; Test Sign Bit
; PRODH = PRODH
PRODH, WREG ;
products
RES2, F
WREG, F
RES3, F
;
;
;
;
- ARG2
ADDWFC
Example 6-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 6-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
Example 6-4 shows the sequence to do an 16 x 16
signed multiply. Equation 6-2 shows the algorithm
used. The 32-bit result is stored in four registers
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs most significant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 6-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EQUATION 6-2: 16 x 16 SIGNED
MULTIPLICATION
RES3:RES0
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
(ARG1H • ARG2H • 2 )+
8
(ARG1H • ARG2L • 2 )+
ALGORITHM
8
(ARG1L • ARG2H • 2 )+
RES3:RES0
(ARG1L • ARG2L)
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
(ARG1H • ARG2H • 2 )+
8
(ARG1H • ARG2L • 2 )+
8
(ARG1L • ARG2H • 2 )+
(ARG1L • ARG2L)+
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 )+
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
16
16
)
DS39026B-page 62
Preliminary
7/99 Microchip Technology Inc.