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PIC18C452-I/L 参数 Datasheet PDF下载

PIC18C452-I/L图片预览
型号: PIC18C452-I/L
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能微控制器,10位A / D [High-Performance Microcontrollers with 10-Bit A/D]
分类和应用: 微控制器
文件页数/大小: 296 页 / 4835 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18CXX2  
The WDT time-out period values may be found in the  
Electrical Specifications section under parameter #31.  
Values for the WDT postscaler may be assigned using  
the configuration bits.  
18.2  
Watchdog Timer (WDT)  
The Watchdog Timer is a free running on-chip RC oscil-  
lator, which does not require any external components.  
This RC oscillator is separate from the RC oscillator of  
the OSC1/CLKI pin. That means that the WDT will run,  
even if the clock on the OSC1/CLKI and OSC2/CLKO/  
RA6 pins of the device has been stopped, for example,  
by execution of a SLEEPinstruction.  
Note: The CLRWDTand SLEEPinstructions clear  
the WDT and the postscaler if assigned to  
the WDT, and prevent it from timing out and  
generating a device RESET condition.  
During normal operation, a WDT time-out generates a  
device RESET (Watchdog Timer Reset). If the device is  
in SLEEP mode, a WDT time-out causes the device to  
wake-up and continue with normal operation (Watch-  
dog Timer Wake-up). The TO bit in the RCON register  
will be cleared upon a WDT time-out.  
Note: When a CLRWDT instruction is executed  
and the prescaler is assigned to the WDT,  
the prescaler count will be cleared, but the  
prescaler assignment is not changed.  
The Watchdog Timer is enabled/disabled by a device  
configuration bit. If the WDT is enabled, software exe-  
cution may not disable this function. When the WDTEN  
configuration bit is cleared, the SWDTEN bit enables/  
disables the operation of the WDT.  
18.2.1 CONTROL REGISTER  
Register 18-7 shows the WDTCON register. This is a  
readable and writable register, which contains a control  
bit that allows software to override the WDT enable  
configuration bit, only when the configuration bit has  
disabled the WDT.  
Register 18-7 WDTCON Register  
U-0  
U-0  
U-0  
U-0  
U-0  
U-0  
U-0  
R/W-0  
SWDTEN  
bit 0  
bit 7  
bit 7:1  
bit 0  
Unimplemented: Read as ’0’  
SWDTEN: Software Controlled Watchdog Timer Enable Bit  
1= Watchdog Timer is on  
0= Watchdog Timer is turned off if the WDTEN configuration bit in the configuration  
register = ’0’  
Legend:  
R = Readable bit  
W = Writable bit  
U = Unimplemented bit, read as ‘0’  
- n = Value at POR reset  
7/99 Microchip Technology Inc.  
Preliminary  
DS39026B-page 185  
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