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PIC18C452-I/L 参数 Datasheet PDF下载

PIC18C452-I/L图片预览
型号: PIC18C452-I/L
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能微控制器,10位A / D [High-Performance Microcontrollers with 10-Bit A/D]
分类和应用: 微控制器
文件页数/大小: 296 页 / 4835 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18CXX2  
18.3.2 WAKE-UP USING INTERRUPTS  
Even if the flag bits were checked before executing a  
SLEEP instruction, it may be possible for flag bits to  
become set before the SLEEPinstruction completes. To  
determine whether a SLEEPinstruction executed, test  
the PD bit. If the PD bit is set, the SLEEP instruction  
was executed as a NOP.  
When global interrupts are disabled (GIE cleared) and  
any interrupt source has both its interrupt enable bit  
and interrupt flag bit set, one of the following will occur:  
• If an interrupt condition (interrupt flag bit and inter-  
rupt enable bits are set) occurs before the execu-  
tion of a SLEEPinstruction, the SLEEPinstruction  
will complete as a NOP. Therefore, the WDT and  
WDT postscaler will not be cleared, the TO bit will  
not be set and PD bits will not be cleared.  
To ensure that the WDT is cleared, a CLRWDTinstruc-  
tion should be executed before a SLEEPinstruction.  
• If the interrupt condition occurs during or after  
the execution of a SLEEPinstruction, the device  
will immediately wake up from sleep. The SLEEP  
instruction will be completely executed before the  
wake-up. Therefore, the WDT and WDT  
postscaler will be cleared, the TO bit will be set  
and the PD bit will be cleared.  
FIGURE 18-3: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
OSC1  
(2)  
(4)  
TOST  
CLKOUT  
INT pin  
INTF flag  
(INTCON<1>)  
(3)  
Interrupt Latency  
GIEH bit  
(INTCON<7>)  
Processor in  
SLEEP  
INSTRUCTION FLOW  
PC  
PC  
PC+2  
PC+4  
PC+4  
PC + 4  
0008h  
000Ah  
Instruction  
Inst(0008h)  
Inst(PC + 2)  
Inst(PC + 4)  
Inst(000Ah)  
Inst(PC) = SLEEP  
Inst(PC - 1)  
fetched  
Instruction  
executed  
Dummy cycle  
Dummy cycle  
SLEEP  
Inst(PC + 2)  
Inst(0008h)  
Note 1: XT, HS or LP oscillator mode assumed.  
2: GIE = '1' assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = '0',  
execution will continue in-line.  
3: TOST = 1024TOSC (drawing not to scale) This delay will not occur for RC and EC osc modes.  
4: CLKOUT is not available in these osc modes, but shown here for timing reference.  
DS39026B-page 188  
Preliminary  
7/99 Microchip Technology Inc.  
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