PIC18F6525/6621/8525/8621
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal oper-
3.0
RESET
The PIC18F6525/6621/8525/8621 devices differentiate
between various kinds of Reset:
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 3-2. These bits
are used in software to determine the nature of the
Reset. See Table 3-3 for a full description of the Reset
states of all registers.
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Timer (WDT) Reset (during normal
operation)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses. The MCLR pin is not driven low by
any internal Resets, including the WDT.
g) Stack Full Reset
h) Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during Sleep and by the
RESETinstruction.
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESETInstruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
WDT
Time-out
Reset
MCLR
WDT
Module
Sleep
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BOR
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
Q
R
OSC1
PWRT
10-bit Ripple Counter
On-chip
RC OSC(1)
Enable PWRT
(2)
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
2005 Microchip Technology Inc.
DS39612B-page 29
MICROCHIP [ MICROCHIP ]
