PIC18F8621-I/PT 参数 Datasheet PDF下载

型号：	PIC18F8621-I/PT
PDF下载：	下载PDF文件查看货源
内容描述：	八十〇分之六十四引脚高性能， 64 KB的增强型闪存微控制器与A / D [64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D]
分类和应用：	闪存微控制器和处理器外围集成电路装置时钟
文件页数/大小：	396 页 / 6639 K
品牌：	MICROCHIP [ MICROCHIP ]

PIC18F6525/6621/8525/8621

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESET Instruction

Stack Resets

FSR1L

PIC18F6X2X PIC18F8X2X

xxxx xxxx

---- 0000

N/A

uuuu uuuu

---- 0000

N/A

uuuu uuuu

---- uuuu

N/A

BSR

INDF2

POSTINC2

POSTDEC2

PREINC2

PLUSW2

FSR2H

N/A

---- 0000

xxxx xxxx

---x xxxx

0000 0000

xxxx xxxx

1111 1111

---- 0000

--00 0101

---- ---0

0--1 11qq

xxxx xxxx

0-00 0000

0000 0000

1111 1111

-000 0000

xxxx xxxx

0000 0000

xxxx xxxx

---- 0000

uuuu uuuu

---u uuuu

uuuu uuuu

1111 1111

---- 0000

--00 0101

---- ---0

0--1 qquu

uuuu uuuu

u-uu uuuu

0000 0000

1111 1111

-000 0000

uuuu uuuu

0000 0000

uuuu uuuu

---- uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

---- uuuu

--uu uuuu

---- ---u

u--1 qquu

uuuu uuuu

u-uu uuuu

uuuu uuuu

-uuu uuuu

uuuu uuuu

FSR2L

STATUS

TMR0H

TMR0L

T0CON

OSCCON

LVDCON

WDTCON

RCON⁽⁴⁾

TMR1H

TMR1L

T1CON

TMR2

PR2

T2CON

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 3-2 for Reset value for specific condition.

5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.

7: If MCLR function is disabled, PORTG<5> is a read-only bit.

8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.

9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode.

 2005 Microchip Technology Inc.

DS39612B-page 33

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