PIC18F6525/6621/8525/8621
TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
INTCON
RCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
0000 000x 0000 000u
0--1 11qq 0--q qquu
IPEN
—
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
—
—
(1)
PIR1
PSPIF
PSPIE
PSPIP
—
RC1IF
RC1IE
RC1IP
—
TX1IF
TX1IE
TX1IP
EEIF
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
TMR4IF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
(1)
(1)
PIE1
IPR1
PIR2
LVDIF
LVDIE
LVDIP
TMR3IF CCP2IF -0-0 0000 ---0 0000
TMR3IE CCP2IE -0-0 0000 ---0 0000
TMR3IP CCP2IP -1-1 1111 ---1 1111
PIE2
—
—
EEIE
EEIP
TX2IF
TX2IE
TX2IP
IPR2
—
—
PIR3
—
RC2IF
RC2IE
RC2IP
CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
PIE3
—
—
TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111
1111 1111 1111 1111
IPR3
—
—
TRISB
PORTB Data Direction Register
PORTC Data Direction Register
PORTE Data Direction Register
TRISC
1111 1111 1111 1111
TRISE
1111 1111 1111 1111
TRISG
—
—
—
---1 1111 ---1 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PORTG Data Direction Register
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
T3CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
CCPR3L
CCPR3H
CCP3CON
CCPR4L
CCPR4H
CCP4CON
CCPR5L
CCPR5H
CCP5CON
Legend:
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Timer3 Register High Byte
Timer3 Register Low Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
Enhanced Capture/Compare/PWM Register 1 Low Byte
Enhanced Capture/Compare/PWM Register 1 High Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
P1M1
P1M0
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
Enhanced Capture/Compare/PWM Register 2 Low Byte
Enhanced Capture/Compare/PWM Register 2 High Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
P2M1
P2M0
DC2B1
DC2B0
CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000
Enhanced Capture/Compare/PWM Register 3 Low Byte
Enhanced Capture/Compare/PWM Register 3 High Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
P3M1
P3M0
DC3B1
DC3B0
CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 4 Low Byte
Capture/Compare/PWM Register 4 High Byte
xxxx xxxx uuuu uuuu
—
—
DC4B1
DC4B0
CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 5 Low Byte
Capture/Compare/PWM Register 5 High Byte
xxxx xxxx uuuu uuuu
—
—
DC5B1
DC5B0
CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 --00 0000
x= unknown, u= unchanged, — = unimplemented, read as ‘0’.
Shaded cells are not used by Capture and Compare, Timer1 or Timer3.
Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
2005 Microchip Technology Inc.
DS39612B-page 153
MICROCHIP [ MICROCHIP ]
