PIC18F2331/2431/4331/4431
TABLE 5-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
Brown-out Reset
WDT Reset
RESETInstruction
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
PTCON0
PTCON1
PTMRL
PTMRH
PTPERL
PTPERH
PDC0L
PDC0H
PDC1L
PDC1H
PDC2L
PDC2H
PDC3L
PDC3H
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
0000 0000
00-- ----
0000 0000
---- 0000
1111 1111
---- 1111
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
---- 0000
-111 0000
0000 0-00
0000 0000
0000 0000
1111 1111
0000 0000
xxxx xxxx
uuuu uuuu
00-- ----
0000 0000
---- 0000
1111 1111
---- 1111
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
--00 0000
0000 0000
---- 0000
-111 0000
0000 0-00
0000 0000
0000 0000
1111 1111
0000 0000
uuuu uuuu
uuuu uuuu
uu-- ----
uuuu uuuu
---- uuuu
uuuu uuuu
---- uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
---- uuuu
-uuu uuuu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
SEVTCMPL 2331 2431 4331 4431
SEVTCMPH 2331 2431 4331 4431
PWMCON0 2331 2431 4331 4431
PWMCON1 2331 2431 4331 4431
DTCON
2331 2431 4331 4431
FLTCONFIG 2331 2431 4331 4431
OVDCOND 2331 2431 4331 4431
OVDCONS
2331 2431 4331 4431
CAP1BUFH/ 2331 2431 4331 4431
VELRH
CAP1BUFL/ 2331 2431 4331 4431
VELRL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
CAP2BUFH/ 2331 2431 4331 4431
POSCNTH
CAP2BUFL/ 2331 2431 4331 4431
POSCNTL
CAP3BUFH/ 2331 2431 4331 4431
MAXCNTH
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 5-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE
pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented.
DS39616D-page 58
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
