PIC18F4431-I/P 参数 Datasheet PDF下载

型号：	PIC18F4431-I/P
PDF下载：	下载PDF文件查看货源
内容描述：	28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术，高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用：	闪存微控制器
文件页数/大小：	392 页 / 3127 K
品牌：	MICROCHIP [ MICROCHIP ]

PIC18F2331/2431/4331/4431

TABLE 5-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets

WDT Reset

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESETInstruction

Stack Resets

IPR2

PIR2

PIE2

IPR1

PIR1

2331 2431 4331 4431

1--1 -1-1

0--0 -0-0

-111 1111

-000 0000

0000 0000

-000 0000

--00 0000

---- -111

1111 1111

1111 1111⁽⁵⁾

1111 1111

---- -xxx

xxxx xxxx

xxxx xxxx⁽⁵⁾

xxxx xxxx

---- xxxx

xxxx xxxx

xx0x 0000⁽⁵⁾

1--1 -1-1

0--0 -0-0

-111 1111

-000 0000

0000 0000

-000 0000

--00 0000

---- -111

1111 1111

1111 1111⁽⁵⁾

1111 1111

---- -uuu

uuuu uuuu

uuuu uuuu⁽⁵⁾

uuuu uuuu

---- xxxx

uuuu uuuu

uu0u 0000⁽⁵⁾

u--u -u-u

-uuu uuuu

-uuu uuuu⁽¹⁾

uuuu uuuu

-uuu uuuu

--uu uuuu

---- -uuu

uuuu uuuu

uuuu uuuu⁽⁵⁾

uuuu uuuu

---- -uuu

uuuu uuuu

uuuu uuuu⁽⁵⁾

uuuu uuuu

---- uuuu

uuuu uuuu

uuuu uuuu⁽⁵⁾

PIE1

OSCTUNE

TRISE⁽⁶⁾

TRISD

TRISC

TRISB

TRISA⁽⁵⁾

PR5H

PR5L

LATE⁽⁶⁾

LATD

LATC

LATB

LATA⁽⁵⁾

TMR5H

TMR5L

PORTE⁽⁶⁾

PORTD

PORTC

PORTB

PORTA⁽⁵⁾

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 5-2 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE

pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented.

 2010 Microchip Technology Inc.

DS39616D-page 57

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