PIC18F2331/2431/4331/4431
TABLE 5-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
Brown-out Reset
WDT Reset
RESETInstruction
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
ADCON3
ADCHS
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
ANSEL1
ANSEL0
T5CON
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
xxxx xxxx
xxxx xxxx
--00 0000
00-0 0000
0000 0000
00-0 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
---- ---1
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
-1-1 0-00
0000 0000
0000 0000
0000 0000
xx-0 x000
---1 1111
---0 0000
---0 0000
uuuu uuuu
uuuu uuuu
--00 0000
00-0 0000
0000 0000
00-0 0000
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
---- ---1
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
-1-1 0-00
0000 0000
0000 0000
0000 0000
uu-0 u000
---1 1111
---0 0000
---0 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
uu-u uuuu
uuuu uuuu
uu-u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
---- ---u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
-u-u u-uu
uuuu uuuu
uuuu uuuu
0000 0000
uu-0 u000
---u uuuu
---u uuuu
---u uuuu
QEICON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
BAUDCON
EEADR
EEDATA
EECON2
EECON1
IPR3
PIE3
PIR3
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 5-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE
pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented.
DS39616D-page 56
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
