PIC18F2331/2431/4331/4431
FIGURE 5-7:
TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note:
TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
TABLE 5-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
Condition
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
0000h
0000h
0000h
0000h
0--1 1100
0--0 uuuu
0--1 11u-
0--u 1uuu
1
0
1
u
1
u
1
1
1
u
1
u
0
u
u
u
0
u
0
u
0
u
u
u
0
u
u
u
RESETInstruction
Brown-out
MCLR Reset during power-managed
Run modes
MCLR Reset during power-managed Idle
and Sleep modes
0000h
0000h
0--u 10uu
0--u 0uuu
u
u
1
0
0
u
u
u
u
u
u
u
u
u
WDT Time-out during full power or
power-managed Run modes
MCLR Reset during full-power execution
Stack Full Reset (STVREN = 1)
u
1
u
u
u
u
1
1
0000h
0000h
0--u uuuu
u
u
u
u
u
Stack Underflow Reset (STVREN = 1)
Stack Underflow Error (not an actual
Reset, STVREN = 0)
u--u uuuu
u--u 00uu
u--u u0uu
u
u
u
u
0
u
u
0
0
u
u
u
u
u
u
WDT time-out during power-managed Idle
or Sleep modes
PC + 2
u
u
u
u
(1)
Interrupt exit from power-managed modes PC + 2
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’.
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
2010 Microchip Technology Inc.
DS39616D-page 53
MICROCHIP [ MICROCHIP ]
