PIC18F2331/2431/4331/4431
FIGURE 26-14:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
77
MSb In
74
bit 6 - - - -1
LSb In
TABLE 26-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS to SCK or SCK Input
TCY
—
ns
TssL2scL
71
TscH
TscL
TB2B
SCK Input High Time
SCK Input Low Time
Continuous
Single byte
Continuous
Single byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
40
75
TdoR
SDO Data Output Rise Time
PIC18FXX31
PIC18LFXX31
—
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
76
77
80
TdoF
SDO Data Output Fall Time
—
25
TssH2doZ SS to SDO Output High-Impedance
10
50
TscH2doV, SDO Data Output Valid after SCK
TscL2doV Edge
PIC18FXX31
PIC18LFXX31
PIC18FXX31
PIC18LFXX31
—
50
—
100
50
82
83
TssL2doV SDO Data Output Valid after SS
—
—
Edge
100
—
TscH2ssH, SS after SCK Edge
1.5 TCY + 40
TscL2ssH
Note 1: Requires the use of Parameter 73A.
2: Only if Parameter 71A and 72A are used.
DS39616D-page 356
2010 Microchip Technology Inc.