PIC18F2331/2431/4331/4431
FIGURE 26-11:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SCK
(CKP = 0)
78
79
SCK
(CKP = 1)
78
79
80
bit 6 - - - - - -1
MSb
LSb
SDO
SDI
75, 76
MSb In
74
bit 6 - - - -1
LSb In
73
TABLE 26-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
73
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
20
—
—
ns
ns
73A
74
Tb2b
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
40
—
ns
75
TdoR
SDO Data Output Rise Time PIC18FXX31
PIC18LFXX31
—
—
—
—
—
—
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TdoF
TscR
SDO Data Output Fall Time
SCK Output Rise Time
SCK Output Fall Time
PIC18FXX31
PIC18LFXX31
79
80
TscF
TscH2doV, SDO Data Output Valid after PIC18FXX31
TscL2doV SCK Edge
PIC18LFXX31
2010 Microchip Technology Inc.
DS39616D-page 353
MICROCHIP [ MICROCHIP ]
