PIC18F2331/2431/4331/4431
TABLE 26-16: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max
Units
Conditions
Clock High Time
4.0
—
s
PIC18FXX31 must operate at
a minimum of 1.5 MHz
100
THIGH
400 kHz mode
0.6
—
s
PIC18FXX31 must operate at
a minimum of 10 MHz
SSP module
1.5 TCY
4.7
—
—
Clock Low Time
100 kHz mode
s
s
PIC18FXX31 must operate at
a minimum of 1.5 MHz
101
TLOW
400 kHz mode
1.3
—
PIC18FXX31 must operate at
a minimum of 10 MHz
SSP Module
1.5 TCY
—
—
SDA and SCL Rise
Time
100 kHz mode
400 kHz mode
1000
300
ns
ns
102
103
TR
TF
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
SDA and SCL Fall
Time
100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1 CB
CB is specified to be from
10 to 400 pF
Start Condition Setup 100 kHz mode
4.7
0.6
4.0
0.6
0
—
—
s
s
s
s
ns
s
ns
ns
s
s
ns
ns
s
s
Only relevant for Repeated
Start condition
90
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
Time
400 kHz mode
Start Condition Hold
Time
100 kHz mode
400 kHz mode
—
After this period, the first clock
pulse is generated
91
—
Data Input Hold Time 100 kHz mode
400 kHz mode
—
106
107
92
0
0.9
—
Data Input Setup
Time
100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
Stop Condition Setup 100 kHz mode
—
Time
400 kHz mode
—
Output Valid From
Clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
(Note 1)
109
110
—
Bus Free Time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
TBUF
—
D102
CB
Bus Capacitive Loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2
2
2: A Fast mode I C bus device can be used in a Standard mode I C bus system, but the requirement, TSU:DAT 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,.
2
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCL line
is released.
DS39616D-page 358
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
