PIC18F2331/2431/4331/4431
FIGURE 26-12:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
81
SCK
(CKP = 0)
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
bit 6 - - - - - -1
SDO
SDI
75, 76
MSb In
74
bit 6 - - - -1
LSb In
TABLE 26-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
73
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
20
—
—
—
ns
ns
ns
73A
74
Tb2b
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 TCY + 40
40
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
75
TdoR
SDO Data Output Rise Time PIC18FXX31
PIC18LFXX31
—
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TdoF
TscR
SDO Data Output Fall Time
—
SCK Output Rise Time
PIC18FXX31
PIC18LFXX31
—
—
79
80
TscF
SCK Output Fall Time
—
TscH2doV, SDO Data Output Valid after PIC18FXX31
TscL2doV SCK Edge
—
PIC18LFXX31
—
81
TdoV2scH, SDO Data Output Setup to SCK Edge
TdoV2scL
TCY
DS39616D-page 354
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
