PIC18F2331/2431/4331/4431
FIGURE 26-13:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
MSb
LSb
SDO
SDI
bit 6 - - - - - -1
bit 6 - - - -1
77
75, 76
MSb In
74
LSb In
73
TABLE 26-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS to SCK or SCK Input
TCY
—
ns
TssL2scL
71
TscH
SCK Input High Time
SCK Input Low Time
Continuous
Single byte
Continuous
Single byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
ns (Note 1)
TscL
1.25 TCY + 30
ns
72A
73
40
20
ns (Note 1)
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
40
ns
75
TdoR
SDO Data Output Rise Time
PIC18FXX31
PIC18LFXX31
—
25
45
25
50
50
100
—
ns
ns
ns
ns
ns
ns
ns
—
76
77
80
TdoF
SDO Data Output Fall Time
—
TssH2doZ SS to SDO Output High-Impedance
10
TscH2doV, SDO Data Output Valid after SCK Edge PIC18FXX31
TscL2doV
—
—
PIC18LFXX31
83
TscH2ssH, SS after SCK Edge
1.5 TCY + 40
TscL2ssH
Note 1: Requires the use of Parameter 73A.
2: Only if Parameter 71A and 72A are used.
2010 Microchip Technology Inc.
DS39616D-page 355
MICROCHIP [ MICROCHIP ]
