PIC18F2331/2431/4331/4431
FIGURE 26-17:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK/SS
Pin
121
121
RC7/RX/DT/SDO
Pin
120
122
TABLE 26-18: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
120
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
PIC18FXX31
PIC18LFXX31
—
—
—
—
—
—
40
100
20
ns
ns
ns
ns
ns
ns
121
122
Tckrf
Tdtrf
Clock Out Rise Time and Fall Time PIC18FXX31
(Master mode)
PIC18LFXX31
PIC18FXX31
PIC18LFXX31
50
Data Out Rise Time and Fall Time
20
50
FIGURE 26-18:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK/SS
Pin
125
RC7/RX/DT/SDO
Pin
126
TABLE 26-19: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data Hold before CK (DT hold time)
10
15
—
—
ns
ns
126
TckL2dtl
Data Hold after CK (DT hold time)
DS39616D-page 360
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
