PIC18F2331/2431/4331/4431
TABLE 26-17: SSP I2C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100
101
102
103
90
THIGH
Clock High Time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
ms
ns
TLOW
TR
Clock Low Time 100 kHz mode
400 kHz mode
—
—
SDA and SCL
Rise Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
1000
300
300
300
—
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
ns
TF
SDA and SCL
Fall Time
—
ns
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
ns
TSU:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ms Only relevant for
Setup Time
Repeated Start
condition
400 kHz mode
—
ms
91
THD:STA Start Condition 100 kHz mode
2(TOSC)(BRG + 1)
—
—
ms After this period, the first
Hold Time
clock pulse is generated
400 kHz mode
2(TOSC)(BRG + 1)
ms
106
107
92
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
0
—
ns
0
0.9
—
ms
TSU:DAT Data Input
Setup Time
250
ns
100
—
ns
TSU:STO Stop Condition
Setup Time
2(TOSC)(BRG + 1)
—
ms
2(TOSC)(BRG + 1)
—
ms
109
110
TAA
Output Valid
from Clock
—
—
3500
1000
—
ns
ns
TBUF
Bus Free Time
4.7
1.3
ms Time the bus must be
free before a new
—
ms
transmission can start
pF
D102 CB
Bus Capacitive Loading
—
400
2010 Microchip Technology Inc.
DS39616D-page 359
MICROCHIP [ MICROCHIP ]
