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PIC18F4431-I/PT 参数 Datasheet PDF下载

PIC18F4431-I/PT图片预览
型号: PIC18F4431-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
setting the IDLEN bit and executing  
a SLEEP  
4.4.1  
PRI_IDLE MODE  
instruction. If the device is in another Run mode, set the  
IDLEN bit first, then set the SCS<1:0> bits to ‘01’ and  
execute SLEEP. When the clock source is switched to  
the Timer1 oscillator, the primary oscillator is shut down,  
the OSTS bit is cleared and the T1RUN bit is set.  
This mode is unique among the three low-power Idle  
modes, in that it does not disable the primary device  
clock. For timing-sensitive applications, this allows for  
the fastest resumption of device operation with its more  
accurate primary clock source, since the clock source  
does not have to “warm-up” or transition from another  
oscillator.  
When a wake event occurs, the peripherals continue to  
be clocked from the Timer1 oscillator. After an interval  
of TCSD, following the wake event, the CPU begins exe-  
cuting code being clocked by the Timer1 oscillator. The  
IDLEN and SCS bits are not affected by the wake-up;  
the Timer1 oscillator continues to run (see Figure 4-8).  
PRI_IDLE mode is entered from PRI_RUN mode by  
setting the IDLEN bit and executing a SLEEP instruc-  
tion. If the device is in another Run mode, set IDLEN  
first, then clear the SCS bits and execute SLEEP.  
Although the CPU is disabled, the peripherals continue  
to be clocked from the primary clock source specified  
by the FOSC<3:0> Configuration bits. The OSTS bit  
remains set (see Figure 4-7).  
Note:  
The Timer1 oscillator should already be  
running prior to entering SEC_IDLE  
mode. If the T1OSCEN bit is not set when  
the SLEEP instruction is executed, the  
SLEEP instruction will be ignored and  
entry to SEC_IDLE mode will not occur. If  
the Timer1 oscillator is enabled but not yet  
running, peripheral clocks will be delayed  
until the oscillator has started. In such  
situations, initial oscillator operation is far  
from stable and unpredictable operation  
may result.  
When a wake event occurs, the CPU is clocked from the  
primary clock source. A delay of interval, TCSD, is  
required between the wake event and when code  
execution starts. This is required to allow the CPU to  
become ready to execute instructions. After the wake-  
up, the OSTS bit remains set. The IDLEN and SCS bits  
are not affected by the wake-up (see Figure 4-8).  
4.4.2  
SEC_IDLE MODE  
In SEC_IDLE mode, the CPU is disabled but the  
peripherals continue to be clocked from the Timer1  
oscillator. This mode is entered from SEC_RUN by  
FIGURE 4-7:  
TRANSITION TIMING FOR ENTRY TO IDLE MODE  
Q3  
Q4  
Q1  
Q1  
Q2  
OSC1  
CPU Clock  
Peripheral  
Clock  
Program  
Counter  
PC  
PC + 2  
FIGURE 4-8:  
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE  
Q1  
Q3  
Q4  
Q2  
OSC1  
TCSD  
CPU Clock  
Peripheral  
Clock  
Program  
Counter  
PC  
Wake Event  
DS39616D-page 44  
2010 Microchip Technology Inc.  
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