PIC18F2331/2431/4331/4431
This section discusses Resets generated by MCLR,
POR and BOR, and the operation of the various start-
up timers. Stack Reset events are covered in
Section 6.1.2.4 “Stack Full/Underflow Resets”.
WDT Resets are covered in Section 23.2 “Watchdog
Timer (WDT)”.
5.0
RESET
The PIC18F2331/2431/4331/4431 devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
g) Stack Full Reset
h) Stack Underflow Reset
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
BOREN
VDD
Brown-out
Reset
S
OST/PWRT
OST
10-Bit Ripple Counter
1024 Cycles
Chip_Reset
R
Q
OSC1
32 s
65.5 ms
PWRT
11-Bit Ripple Counter
INTRC
Enable PWRT
(1)
Enable OST
Note 1: See Table 5-1 for time-out situations.
2010 Microchip Technology Inc.
DS39616D-page 47
MICROCHIP [ MICROCHIP ]
