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PIC18F4431-I/PT 参数 Datasheet PDF下载

PIC18F4431-I/PT图片预览
型号: PIC18F4431-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
If the IRCF bits and the INTSRC bit are all clear, the  
INTOSC output is not enabled and the IOFS bit will  
remain clear; there will be no indication of the current  
clock source. The INTRC source is providing the  
device clocks.  
On transitions from RC_RUN mode to PRI_RUN mode,  
the device continues to be clocked from the INTOSC  
multiplexer while the primary clock is started. When the  
primary clock becomes ready, a clock switch to the  
primary clock occurs (see Figure 4-4). When the clock  
switch is complete, the IOFS bit is cleared, the OSTS  
bit is set and the primary clock is providing the device  
clock. The IDLEN and SCS bits are not affected by the  
switch. The INTRC source will continue to run if either  
the WDT or the Fail-Safe Clock Monitor is enabled.  
If the IRCF bits are changed from all clear (thus,  
enabling the INTOSC output), or if INTSRC is set, the  
IOFS bit becomes set after the INTOSC output  
becomes stable. Clocks to the device continue while  
the INTOSC source stabilizes, after an interval of  
TIOBST.  
If the IRCF bits were previously at a non-zero value, or  
if INTSRC was set before setting SCS1 and the  
INTOSC source was already stable, the IOFS bit will  
remain set.  
FIGURE 4-3:  
TRANSITION TIMING TO RC_RUN MODE  
Q1 Q2 Q3 Q4 Q1  
Q2  
Q3  
Q4  
Q1  
Q2  
Q3  
1
2
3
n-1  
n
INTRC  
OSC1  
Clock Transition(1)  
CPU  
Clock  
Peripheral  
Clock  
Program  
Counter  
PC  
PC + 2  
PC + 4  
Note 1: Clock transition typically occurs within 2-4 TOSC.  
FIGURE 4-4:  
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE  
Q3  
Q4  
Q1  
Q2 Q3 Q4 Q1 Q2 Q3  
Q1  
Q2  
INTOSC  
Multiplexer  
OSC1  
(1)  
TOST  
(1)  
TPLL  
1
2
n-1  
n
PLL Clock  
Output  
Clock  
Transition(2)  
CPU Clock  
Peripheral  
Clock  
Program  
Counter  
PC  
PC + 2  
PC + 4  
SCS<1:0> bits Changed  
OSTS bit Set  
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.  
2: Clock transition typically occurs within 2-4 TOSC.  
DS39616D-page 42  
2010 Microchip Technology Inc.  
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