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PIC18F4431-I/PT 参数 Datasheet PDF下载

PIC18F4431-I/PT图片预览
型号: PIC18F4431-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
FIGURE 4-1:  
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE  
Q1 Q2 Q3 Q4 Q1  
Q2  
Q3  
Q4  
Q1  
Q2  
Q3  
1
2
3
n-1  
n
T1OSI  
Clock Transition(1)  
OSC1  
CPU  
Clock  
Peripheral  
Clock  
Program  
Counter  
PC  
PC + 2  
PC + 4  
Note 1: Clock transition typically occurs within 2-4 TOSC.  
FIGURE 4-2:  
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)  
Q1  
Q2  
Q3  
Q4  
Q1  
Q2 Q3 Q4 Q1 Q2 Q3  
T1OSI  
OSC1  
(1)  
TOST  
(1)  
TPLL  
1
2
n-1  
n
PLL Clock  
Output  
Clock  
Transition(2)  
CPU Clock  
Peripheral  
Clock  
Program  
Counter  
PC + 2  
PC + 4  
PC  
SCS<1:0> bits Changed  
OSTS bit Set  
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.  
2: Clock transition typically occurs within 2-4 TOSC.  
This mode is entered by setting the SCS1 bit to ‘1’.  
4.2.3  
RC_RUN MODE  
Although it is ignored, it is recommended that the SCS0  
bit also be cleared; this is to maintain software compat-  
ibility with future devices. When the clock source is  
switched to the INTOSC multiplexer (see Figure 4-3),  
the primary oscillator is shut down and the OSTS bit is  
cleared. The IRCF bits may be modified at any time to  
immediately change the clock speed.  
In RC_RUN mode, the CPU and peripherals are  
clocked from the internal oscillator block using the  
INTOSC multiplexer. In this mode, the primary clock is  
shut down. When using the INTRC source, this mode  
provides the best power conservation of all the Run  
modes, while still executing code. It works well for user  
applications which are not highly timing-sensitive or do  
not require high-speed clocks at all times.  
Note:  
Caution should be used when modifying a  
single IRCF bit. If VDD is less than 3V, it is  
possible to select a higher clock speed  
than is supported by the low VDD.  
Improper device operation may result if  
the VDD/FOSC specifications are violated.  
If the primary clock source is the internal oscillator block  
(either INTRC or INTOSC), there are no distinguishable  
differences between PRI_RUN and RC_RUN modes  
during execution. However, a clock switch delay will  
occur during entry to and exit from RC_RUN mode.  
Therefore, if the primary clock source is the internal  
oscillator block, the use of RC_RUN mode is not  
recommended.  
2010 Microchip Technology Inc.  
DS39616D-page 41  
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