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PIC18F4431-I/PT 参数 Datasheet PDF下载

PIC18F4431-I/PT图片预览
型号: PIC18F4431-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
4.1.3  
CLOCK TRANSITIONS AND STATUS  
INDICATORS  
4.2  
Run Modes  
In the Run modes, clocks to both the core and  
peripherals are active. The difference between these  
modes is the clock source.  
The length of the transition between clock sources is  
the sum of two cycles of the old clock source and three  
to four cycles of the new clock source. This formula  
assumes that the new clock source is stable.  
4.2.1  
PRI_RUN MODE  
Three bits indicate the current clock source and its  
status. They are:  
The PRI_RUN mode is the normal, full-power execu-  
tion mode of the microcontroller. This is also the default  
mode upon a device Reset unless Two-Speed Start-up  
is enabled (see Section 23.3 “Two-Speed Start-up”  
for details). In this mode, the OSTS bit is set. The IOFS  
bit may be set if the internal oscillator block is the  
primary clock source (see Section 3.7.1 “Oscillator  
Control Register”).  
• OSTS (OSCCON<3>)  
• IOFS (OSCCON<2>)  
• T1RUN (T1CON<6>)  
In general, only one of these bits will be set while in a  
given power-managed mode. When the OSTS bit is  
set, the primary clock is providing the device clock.  
When the IOFS bit is set, the INTOSC output is  
providing a stable, 8 MHz clock source to a divider that  
actually drives the device clock. When the T1RUN bit is  
set, the Timer1 oscillator is providing the clock. If none  
of these bits are set, then either the INTRC clock  
source is clocking the device, or the INTOSC source is  
not yet stable.  
4.2.2  
SEC_RUN MODE  
The SEC_RUN mode is the compatible mode to the  
“clock switching” feature offered in other PIC18  
devices. In this mode, the CPU and peripherals are  
clocked from the Timer1 oscillator. This gives users the  
option of lower power consumption while still using a  
high-accuracy clock source.  
If the internal oscillator block is configured as the primary  
clock source by the FOSC<3:0> Configuration bits, then  
both the OSTS and IOFS bits may be set when in  
PRI_RUN or PRI_IDLE modes. This indicates that the  
primary clock (INTOSC output) is generating a stable,  
8 MHz output. Entering another power-managed RC  
mode at the same frequency would clear the OSTS bit.  
SEC_RUN mode is entered by setting the SCS<1:0>  
bits to ‘01’. The device clock source is switched to the  
Timer1 oscillator (see Figure 4-1), the primary oscillator  
is shut down, the T1RUN bit (T1CON<6>) is set and the  
OSTS bit is cleared.  
Note:  
The Timer1 oscillator should already be  
running prior to entering SEC_RUN  
mode. If the T1OSCEN bit is not set when  
the SCS<1:0> bits are set to ‘01’, entry to  
SEC_RUN mode will not occur. If the  
Timer1 oscillator is enabled, but not yet  
running, device clocks will be delayed until  
the oscillator has started. In such situa-  
tions, initial oscillator operation is far from  
stable and unpredictable operation may  
result.  
Note 1: Caution should be used when modifying  
a single IRCF bit. If VDD is less than 3V, it  
is possible to select a higher clock speed  
than is supported by the low VDD.  
Improper device operation may result if  
the VDD/FOSC specifications are violated.  
2: Executing a SLEEP instruction does not  
necessarily place the device into Sleep  
mode. It acts as the trigger to place the  
controller into either the Sleep mode or  
one of the Idle modes, depending on the  
setting of the IDLEN bit.  
On transitions from SEC_RUN mode to PRI_RUN, the  
peripherals and CPU continue to be clocked from the  
Timer1 oscillator while the primary clock is started.  
When the primary clock becomes ready, a clock switch  
back to the primary clock occurs (see Figure 4-2).  
When the clock switch is complete, the T1RUN bit is  
cleared, the OSTS bit is set and the primary clock is  
providing the clock. The IDLEN and SCS bits are not  
affected by the wake-up; the Timer1 oscillator  
continues to run.  
4.1.4  
MULTIPLE SLEEP COMMANDS  
The power-managed mode that is invoked with the  
SLEEP instruction is determined by the setting of the  
IDLEN bit at the time the instruction is executed. If  
another SLEEPinstruction is executed, the device will  
enter the power-managed mode specified by IDLEN at  
that time. If IDLEN has changed, the device will enter  
the new power-managed mode specified by the new  
setting.  
DS39616D-page 40  
2010 Microchip Technology Inc.  
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