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PIC18F4431-I/PT 参数 Datasheet PDF下载

PIC18F4431-I/PT图片预览
型号: PIC18F4431-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
In these instances, the primary clock source either  
does not require an oscillator start-up delay since it is  
already running (PRI_IDLE), or normally does not  
require an oscillator start-up delay (RC, EC and INTIO  
Oscillator modes). However, a fixed delay of interval,  
TCSD, following the wake event, is still required when  
leaving Sleep and Idle modes to allow the CPU to  
prepare for execution. Instruction execution resumes  
on the first clock cycle following this delay.  
4.5.4  
EXIT WITHOUT AN OSCILLATOR  
START-UP DELAY  
Certain exits from power-managed modes do not  
invoke the OST at all. There are two cases:  
• PRI_IDLE mode, where the primary clock source  
is not stopped; and  
• the primary clock source is not any of the LP, XT,  
HS or HSPLL modes.  
TABLE 4-2:  
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE  
(BY CLOCK SOURCES)  
Clock Source  
Before Wake-up  
Clock Source  
After Wake-up  
Clock Ready Status  
Bit (OSCCON)  
Exit Delay  
LP, XT, HS  
HSPLL  
OSTS  
IOFS  
OSTS  
IOFS  
OSTS  
IOFS  
OSTS  
IOFS  
Primary Device Clock  
(PRI_IDLE mode)  
(1)  
TCSD  
EC, RC  
INTOSC(2)  
LP, XT, HS  
HSPLL  
(3)  
TOST  
(3)  
TOST + trc  
T1OSC  
(1)  
EC, RC  
TCSD  
INTOSC(2)  
LP, XT, HS  
HSPLL  
TIOBST  
(4)  
(3)  
TOST  
(3)  
TOST + trc  
INTOSC(3)  
(1)  
EC, RC  
TCSD  
INTOSC(2)  
LP, XT, HS  
HSPLL  
None  
(3)  
TOST  
(3)  
TOST + trc  
None  
(Sleep mode)  
(1)  
EC, RC  
INTOSC(2)  
TCSD  
(4)  
TIOBST  
Note 1: TCSD (Parameter 38) is a required delay when waking from Sleep and all Idle modes, and runs concur-  
rently with any other required delays (see Section 4.4 “Idle Modes”).  
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.  
3: TOST is the Oscillator Start-up Timer (Parameter 32). trc is the PLL Lock-out Timer (Parameter F12); it is  
also designated as TPLL.  
4: Execution continues during TIOBST (Parameter 39), the INTOSC stabilization period.  
DS39616D-page 46  
2010 Microchip Technology Inc.  
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