PIC18F2220/2320/4220/4320
FIGURE 26-19:
MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
Stop
Condition
Start
Condition
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-20: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start condition 100 kHz mode
Setup time 400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start condition
1 MHz mode(1) 2(TOSC)(BRG + 1)
91
92
93
THD:STA Start condition 100 kHz mode
Hold time 400 kHz mode
2(TOSC)(BRG + 1)
ns After this period, the first
clock pulse is generated
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
TSU:STO Stop condition 100 kHz mode
Setup time 400 kHz mode
2(TOSC)(BRG + 1)
ns
ns
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
THD:STO Stop condition 100 kHz mode
Hold time 400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
FIGURE 26-20:
MASTER SSP I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 26-5 for load conditions.
DS39599C-page 338
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
