PIC18F2220/2320/4220/4320
FIGURE 26-15:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
80
78
MSb
LSb
SDO
SDI
bit 6 - - - - - -1
77
75, 76
LSb In
MSb In
74
bit 6 - - - -1
73
Note:
Refer to Figure 26-5 for load conditions.
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
SCK Input High Time (Slave mode)
SCK Input Low Time (Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LFXX20
76
77
78
TDOF
SDO Data Output Fall Time
—
10
—
TSSH2DOZ SS ↑ to SDO Output High-Impedance
TSCR
SCK Output Rise Time (Master mode) PIC18FXX20
PIC18LFXX20
79
80
TSCF
SCK Output Fall Time (Master mode)
—
—
TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXX20
TSCL2DOV
PIC18LFXX20
83
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
DS39599C-page 334
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
