PIC18F2220/2320/4220/4320
TABLE 26-19: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
THIGH
Clock High Time
4.0
—
µs
PIC18FXX20 must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
µs
PIC18FXX20 must operate at a
minimum of 10 MHz
SSP module
1.5 TCY
4.7
—
—
101
TLOW
Clock Low Time
100 kHz mode
µs
µs
PIC18FXX20 must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC18FXX20 must operate at a
minimum of 10 MHz
SSP module
1.5 TCY
—
1000
300
300
300
—
102
103
90
TR
TF
SDA and SCL Rise
Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
ns
ns
ns
ns
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
pF
20 + 0.1 CB
CB is specified to be from 10 to 400 pF
CB is specified to be from 10 to 400 pF
SDA and SCL Fall
Time
—
20 + 0.1 CB
TSU:STA Start Condition Setup 100 kHz mode
4.7
0.6
4.0
0.6
0
Only relevant for Repeated
Start condition
Time
400 kHz mode
—
91
THD:STA Start Condition Hold 100 kHz mode
—
After this period, the first clock pulse is
generated
Time
400 kHz mode
—
106
107
92
THD:DAT Data Input Hold Time 100 kHz mode
400 kHz mode
—
0
0.9
—
TSU:DAT Data Input Setup
Time
100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
TSU:STO Stop Condition Setup 100 kHz mode
—
Time
400 kHz mode
—
109
110
D102
TAA
TBUF
CB
Output Valid from
Clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
(Note 1)
—
Bus Free Time
4.7
1.3
—
—
Time the bus must be free before a
new transmission can start
—
Bus Capacitive Loading
400
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2
2
2: A fast mode I C bus device can be used in a standard mode I C bus system but the requirement, TSU:DAT ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,
2
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I C bus specification), before the SCL line
is released.
2003 Microchip Technology Inc.
DS39599C-page 337
MICROCHIP [ MICROCHIP ]
