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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
TABLE 26-21: MASTER SSP I2C BUS DATA REQUIREMENTS  
Param.  
No.  
Symbol  
Characteristic  
Min  
Max Units  
Conditions  
100  
101  
102  
103  
90  
THIGH  
Clock High Time  
Clock Low Time  
100 kHz mode 2(TOSC)(BRG + 1)  
400 kHz mode 2(TOSC)(BRG + 1)  
1 MHz mode(1) 2(TOSC)(BRG + 1)  
100 kHz mode 2(TOSC)(BRG + 1)  
400 kHz mode 2(TOSC)(BRG + 1)  
1 MHz mode(1) 2(TOSC)(BRG + 1)  
ms  
ms  
ms  
ms  
ms  
ms  
TLOW  
TR  
SDA and SCL  
Rise Time  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
1000  
300  
300  
300  
300  
100  
ns CB is specified to be from  
10 to 400 pF  
20 + 0.1 CB  
ns  
ns  
TF  
SDA and SCL  
Fall Time  
20 + 0.1 CB  
ns CB is specified to be from  
10 to 400 pF  
ns  
ns  
TSU:STA Start Condition  
Setup Time  
100 kHz mode 2(TOSC)(BRG + 1)  
400 kHz mode 2(TOSC)(BRG + 1)  
1 MHz mode(1) 2(TOSC)(BRG + 1)  
100 kHz mode 2(TOSC)(BRG + 1)  
400 kHz mode 2(TOSC)(BRG + 1)  
1 MHz mode(1) 2(TOSC)(BRG + 1)  
ms Only relevant for  
Repeated Start condition  
ms  
ms  
91  
THD:STA Start Condition  
Hold Time  
ms After this period, the first  
clock pulse is generated  
ms  
ms  
106  
107  
92  
THD:DAT Data Input  
Hold Time  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
0
ns  
0
0.9  
ms  
TBD  
250  
100  
TBD  
ns  
TSU:DAT Data Input  
Setup Time  
ns (Note 2)  
ns  
ns  
TSU:STO Stop Condition  
Setup Time  
100 kHz mode 2(TOSC)(BRG + 1)  
400 kHz mode 2(TOSC)(BRG + 1)  
1 MHz mode(1) 2(TOSC)(BRG + 1)  
ms  
ms  
ms  
109  
110  
D102  
TAA  
TBUF  
CB  
Output Valid from  
Clock  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
100 kHz mode  
400 kHz mode  
1 MHz mode(1)  
3500  
1000  
ns  
ns  
ns  
Bus Free Time  
4.7  
1.3  
TBD  
ms Time the bus must be free  
before a new transmission  
ms  
can start  
ms  
Bus Capacitive Loading  
400  
pF  
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.  
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 250 ns,  
must then be met. This will automatically be the case if the device does not stretch the LOW period of the  
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit  
to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the  
SCL line is released.  
2003 Microchip Technology Inc.  
DS39599C-page 339  
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