PIC18F2220/2320/4220/4320
FIGURE 26-16:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
77
MSb In
74
bit 6 - - - -1
LSb In
Note: Refer to Figure 26-5 for load conditions.
TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
ns
71
TSCH
TSCL
TB2B
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCK Input Low Time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
—
25
45
25
50
25
45
25
50
100
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LFXX20
76
77
78
TDOF
SDO Data Output Fall Time
—
TSSH2DOZ SS↑ to SDO Output High-Impedance
10
TSCR
SCK Output Rise Time
(Master mode)
PIC18FXX20
—
PIC18LFXX20
—
79
80
TSCF
SCK Output Fall Time (Master mode)
—
TSCH2DOV, SDO Data Output Valid after SCK PIC18FXX20
TSCL2DOV Edge
—
PIC18LFXX20
—
82
83
TSSL2DOV SDO Data Output Valid after SS ↓ PIC18FXX20
—
—
Edge
PIC18LFXX20
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
2003 Microchip Technology Inc.
DS39599C-page 335
MICROCHIP [ MICROCHIP ]
