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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
is tri-stated, even if in the middle of a transmitted byte.  
External pull-up/pull-down resistors may be desirable,  
depending on the application.  
17.3.6  
SLAVE MODE  
In Slave mode, the data is transmitted and received as  
the external clock pulses appear on SCK. When the  
last bit is latched, the SSPIF interrupt flag bit is set.  
Note 1: When the SPI is in Slave mode with SS pin  
control enabled (SSPCON1<3:0> = 0100),  
the SPI module will reset when the SS pin is  
set high.  
While in Slave mode, the external clock is supplied by  
the external clock source on the SCK pin. This external  
clock must meet the minimum high and low times as  
specified in the electrical specifications.  
2: If the SPI is used in Slave mode with CKE  
set, then the SS pin control must be  
enabled.  
While in power managed modes, the slave can trans-  
mit/receive data. When a byte is received, the device  
will wake-up from power managed modes.  
When the SPI module resets, SSPSR is cleared. This  
can be done by either driving the SS pin to a high level  
or clearing the SSPEN bit.  
17.3.7  
SLAVE SELECT CONTROL  
The SS pin allows a master controller to select one of  
several slave controllers for communications in sys-  
tems with more than one slave. The SPI must be in  
Slave mode with SS pin control enabled  
(SSPCON1<3:0> = 04h). The SS pin is configured for  
input by setting TRISA<5>. When the SS pin is low,  
transmission and reception are enabled and the SDO  
pin is driven. When the SS pin goes high, the SDO pin  
To emulate two-wire communication, the SDO pin can  
be connected to the SDI pin. When the SPI needs to  
operate as a receiver the SDO pin can be configured as  
an input. This disables transmissions from the SDO.  
The SDI can always be left as an input (SDI function)  
since it cannot create a bus conflict.  
FIGURE 17-4:  
SLAVE SYNCHRONIZATION WAVEFORM  
SS  
SCK  
(CKP = 0  
CKE = 0)  
SCK  
(CKP = 1  
CKE = 0)  
Write to  
SSPBUF  
bit 6  
bit 7  
bit 7  
bit 0  
bit 0  
SDO  
bit 7  
SDI  
(SMP = 0)  
bit 7  
Input  
Sample  
(SMP = 0)  
SSPIF  
Interrupt  
Flag  
Next Q4 Cycle  
after Q2↓  
SSPSR to  
SSPBUF  
2003 Microchip Technology Inc.  
DS39599C-page 161  
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