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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
Figure 17-3, Figure 17-5 and Figure 17-6, where the  
MSB is transmitted first. In Master mode, the SPI clock  
rate (bit rate) is user programmable to be one of the  
following:  
17.3.5  
MASTER MODE  
The master can initiate the data transfer at any time  
because it controls the SCK. The master determines  
when the slave (Processor 2, Figure 17-2) is to  
broadcast data by the software protocol.  
• FOSC/4 (or TCY)  
• FOSC/16 (or 4 • TCY)  
• FOSC/64 (or 16 • TCY)  
• (Timer2 output)/2  
In Master mode, the data is transmitted/received as  
soon as the SSPBUF register is written to. If the SPI is  
only going to receive, the SDO output could be dis-  
abled (programmed as an input). The SSPSR register  
will continue to shift in the signal present on the SDI pin  
at the programmed clock rate. As each byte is  
received, it will be loaded into the SSPBUF register as  
if a normal received byte (interrupts and status bits  
appropriately set). This could be useful in receiver  
applications as a “Line Activity Monitor” mode.  
The maximum data rate is approximately 3.0 Mbps,  
limited by timing requirements (see Table 26-14  
through Table 26-17).  
Figure 17-3 shows the waveforms for Master mode.  
When the CKE bit is set, the SDO data is valid before  
there is a clock edge on SCK. The change of the input  
sample is shown based on the state of the SMP bit. The  
time when the SSPBUF is loaded with the received  
data is shown.  
The clock polarity is selected by appropriately program-  
ming the CKP bit (SSPCON1<4>). This then, would  
give waveforms for SPI communication as shown in  
FIGURE 17-3:  
SPI MODE WAVEFORM (MASTER MODE)  
Write to  
SSPBUF  
SCK  
(CKP = 0  
CKE = 0)  
SCK  
(CKP = 1  
CKE = 0)  
4 Clock  
Modes  
SCK  
(CKP = 0  
CKE = 1)  
SCK  
(CKP = 1  
CKE = 1)  
bit 6  
bit 6  
bit 2  
bit 2  
bit 5  
bit 5  
bit 4  
bit 4  
bit 1  
bit 1  
bit 0  
bit 0  
SDO  
(CKE = 0)  
bit 7  
bit 7  
bit 3  
bit 3  
SDO  
(CKE = 1)  
SDI  
(SMP = 0)  
bit 0  
bit 7  
Input  
Sample  
(SMP = 0)  
SDI  
(SMP = 1)  
bit 0  
bit 7  
Input  
Sample  
(SMP = 1)  
SSPIF  
Next Q4 Cycle  
after Q2↓  
SSPSR to  
SSPBUF  
DS39599C-page 160  
2003 Microchip Technology Inc.  
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