PIC18F2220/2320/4220/4320
17.3.8
MASTER IN POWER MANAGED
MODES
17.3.8.1
Slave in Power Managed Modes
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in any power managed mode and
data to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the MSSP
interrupt flag bit will be set and if MSSP interrupts are
enabled, will wake the device from a power managed
mode.
In Master mode, module clocks may be operating at a
different speed than when in full power mode, or in the
case of the Sleep Power Managed mode, all clocks are
halted.
In most power managed modes, a clock is provided to
the peripherals and is derived from the primary clock
source, the secondary clock (Timer1 oscillator at 32.768
kHz) or the internal oscillator block (one of eight frequen-
cies between 31 kHz and 8 MHz). See Section 2.7
“Clock Sources and Oscillator Switching” for
additional information.
17.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
17.3.10 BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
If MSSP interrupts are enabled, they can wake the con-
troller from a power managed mode when the master
completes sending data. If an exit from a power
managed mode is not desired, MSSP interrupts should
be disabled.
TABLE 17-1: SPI BUS MODES
Control Bits State
Standard SPI Mode
Terminology
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will pause until
the device wakes from the power managed mode. After
the device returns to full power mode, the module will
resume transmitting and receiving data.
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
There is also an SMP bit which controls when the data
is sampled.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
1111 1111 1111 1111
(1)
PIE1
PSPIE
(1)
IPR1
PSPIP
TRISC
SSPBUF
SSPCON1
TRISA
SSPSTAT
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
PORTA Data Direction Register
D/A
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
SSPM0 0000 0000 0000 0000
(1)
(1)
TRISA7
SMP
TRISA6
CKE
--11 1111 --11 1111
P
S
R/W
UA
BF
0000 0000 0000 0000
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
2003 Microchip Technology Inc.
DS39599C-page 163
MICROCHIP [ MICROCHIP ]
